New Delhi: Union Minister for Electronics and Information Technology Ashwini Vaishnaw interacted with companies engaged in semiconductor chip design that have been approved under the Design Linked Incentive (DLI) Scheme of the Semicon India Programme.
The interaction focused on reviewing progress, assessing innovation outcomes, and reaffirming the government’s commitment to strengthening India’s indigenous semiconductor chip design ecosystem.
The Design Linked Incentive Scheme has been structured to accelerate domestic semiconductor chip design capabilities by supporting startups and companies working across system-on-chips (SoCs), telecom, power management, artificial intelligence, and Internet of Things (IoT) technologies.
The initiative aims to enhance India’s self-reliance in critical semiconductor technologies through long-term, ecosystem-driven support.
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Semiconductor Chip Design Progress Across Strategic Sectors
Companies supported under the DLI Scheme are actively engaged in semiconductor chip design across a wide range of applications, including indigenous SoCs and ASICs for surveillance, networking, and embedded systems.
Their work also spans RISC-V–based processors and accelerators, AI-enabled low-power chips for IoT and edge computing, telecom and wireless chipsets, power management ICs, and mixed-signal designs.
These efforts extend to strategic sectors such as automotive, energy, space, and defence, contributing to the development of a self-reliant and secure semiconductor design ecosystem in India.
Advanced Electronic Design Automation (EDA) tools have been made available to participating organisations, resulting in approximately 2.25 crore tool-hours of usage. Over 67,000 students and more than 1,000 startup engineers are actively engaged through this support.
In academia, 122 designs have been taped out, with 56 chips fabricated at the 180-nanometre node at SCL, Mohali.
Startups have completed 16 tape-outs, leading to the fabrication of six chips at advanced foundry nodes as advanced as 12 nanometres. Additionally, 75 patents have been filed by academic institutions and 10 patents by startups.
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Government’s Long-Term Vision for Semiconductor Chip Design
Addressing stakeholders, Vaishnaw said the government’s multi-year and ecosystem-driven approach to semiconductor development is delivering measurable outcomes.
He noted that the programme was conceptualised in 2022 with a clear vision articulated by Prime Minister Narendra Modi to build the entire semiconductor ecosystem, pursue a long-term strategy, and transform India from a services-led economy into a product-driven nation.
Highlighting the progress of the Design Linked Incentive Scheme, the Minister observed that while expectations were initially modest, the programme now supports 24 startups, many of which have completed tape-outs, validated products, and achieved early market traction.
He stated that this progress validates the government’s approach of removing key barriers for semiconductor startups by enabling access to advanced design tools, IP libraries, wafer fabrication, and tape-out support.
Semiconductor Chip Design: Target to Enable 50 Fabless Companies in Next Phase
The Minister underlined that the comprehensive support provided by the India Semiconductor Mission to startups engaged in semiconductor chip design is globally distinctive.
He announced that the government plans to scale up the programme, with a target of enabling at least 50 fabless semiconductor companies in the next phase. He expressed confidence that India will see the emergence of globally competitive fabless companies comparable to leading international players.
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Focus on Six Core Semiconductor Design Domains
Outlining a focused roadmap, the Minister highlighted six key system categories central to India’s semiconductor chip design strategy – compute systems, RF and wireless, networking, power management, sensors, and memory.
He stated that these categories form the foundational building blocks for modern electronic systems and will enable India to design solutions for defence, space, automotive, railways, drones, and other strategic applications.
On infrastructure development, Vaishnaw stated that SCL Mohali will continue to support tape-outs at the 180-nanometre node, while advanced nodes up to 28 nanometres will be enabled through the upcoming fabrication facility at Dholera. This manufacturing capability will complement domestic design strengths.
He also highlighted the government’s sustained focus on talent development, noting that against a target of training 85,000 skilled professionals over ten years, more than 67,000 semiconductor professionals have already been trained within four years.
Roadmap Towards Global Semiconductor Leadership
Expressing confidence in India’s expanding role in the global semiconductor ecosystem, the Minister said a significant share of global semiconductor design activity would be carried out in India in the coming years.
He added that by 2029, India is expected to achieve the capability to design and manufacture chips required for nearly 70–75 per cent of domestic applications.
Looking ahead, the next phase under Semicon 2.0 will focus on advanced manufacturing, with a roadmap to achieve 3-nanometre and 2-nanometre technology nodes. By 2035, India aims to be among the world’s leading semiconductor nations.
Startup Funding and Deep Tech Awards Announcement
The Minister noted that startups supported under the DLI Scheme have attracted nearly ₹430 crore in venture capital funding, with 14 of the 24 participating startups securing external investments.
He added that the India Semiconductor Mission has delivered strong outcomes, including 10 projects currently under construction and four projects expected to begin production this year. In total, 67,000 students have been trained in semiconductor chip design across 315 academic institutions.
He also announced that the government will institute Deep Tech Awards in 2026 to recognise innovation across key domains such as semiconductors, artificial intelligence, biotechnology, space, and other deep-tech sectors. The first round of awards is expected to be held towards the end of the year.
During the interaction, several startups showcased their tape-out milestones and commercialisation roadmaps enabled by funding and EDA tool support under the DLI Scheme. The event was attended by Secretary, MeitY, S Krishnan, and CEO, India Semiconductor Mission, Amitesh Kumar Sinha.
